The present invention relates to electronics and, more particularly, to integrated circuit memory devices. A major objective of the present invention is to provide for faster and higher density SRAM devices.
Recent technological progress has been closely identified with the development of high-speed, high-density integrated circuits. Among the most prevalent of integrated circuit devices are random access memories (RAMs). RAMs are typically divided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). DRAMs have the advantages of relatively low cost and relatively high density, but require refresh cycles which incur speed and power penalties.
SRAMs are favored where memory access times must be kept to a minimum. An increasingly common computer architecture uses high-density DRAM memory for bulk memory and SRAM as cache memory to speed access to the most commonly used operations and data. SRAMs also have relatively low power requirements and are commonly used in battery powered units, including portable computers.
A conventional SRAM architecture includes an array of memory cells arranged in rows and columns. Data is communicated to and from the memory device via data ports. Cells are selected as a function of address codes received at address inputs. Read and write operations are selected at control inputs. In addition, power and ground, for example, nominal 5 V and 0 V, respectively, are supplied at respective terminals. An address decoder decodes received addresses into control signals that implement the desired cell selection. The address decoder transmits signals along word lines which coupled cells in a row to respective true and false bit lines of a selected column. Some recent devices use divided word line architectures which separate the cell array into blocks to reduce capactive loading on the (sub)word lines. The address decoder also transmits signals to column pass gates or column transmission gates to couple selected bit lines to respective sense amplifiers and thence to the data ports.
SRAM devices generally include transistors fabricated using MOS technology. ("MOS" orginally described transistor gates which were fabricated using metal over a thin oxide layer; today, the term is applied more broadly to include transistors with gates of polysilicon over oxide). NMOS, PMOS and CMOS are three types of MOS technology. "NMOS" refers to n-type MOS transistors; "n-type" refers to a dopant introduced into silicon to enhance its ability to conduct electrons, which are negatively charged particles. "PMOS" uses p-type dopant which enhances the conduction of electron "holes", which are positive charges. "CMOS" means "complementary" MOS and involves the fabrication of both PMOS and NMOS devices on a single substrate. Usually, PMOS devices are fabricated in n-type wells while NMOS devices are formed within the primarily p-type substrate. NMOS has long prevailed over PMOS as a technology of choice, while CMOS has advanced rapidly as the advantages of combining PMOS and NMOS have often outweighed the complexity of combining them.
A MOS transistor includes a gate, a source and a drain. The gate typically acts as the control input to break or complete the electrical path between the source and the drain. In the case of the more common NMOS transistor, a voltage high at the gate closes, i.e., activates the transistor, provided the gate voltage exceeds the source voltage by at least a threshold voltage Vt, typically about 1 V; a voltage low at the gate opens, i.e., deactivates the transistor. In the case of the PMOS transistor, a voltage low at the gate closes the transistor, provided the source voltage exceeds the gate voltage by at least a threshold voltage Vt.
One typical SRAM memory cell design employs complementary, i.e., "true" and "false", pairs of NMOS transistors. Each pair includes a "state" transistor and an "access" transistor. Each state transistor has its source tied to ground; its source and gate are coupled respectively to the gate and source of the other pair. This arrangement tends to force the state transistors into complementary states. For example, a logic high at the source of the true state transistor implies a logic high at the gate of the false state transistor, which is thus closed. The source of the false state transistor is thus coupled to the drain of the false state transistor, and thus to ground. Therefore, the gate of the true transistor is held low so that the true transistor remains open and its source remains decoupled from ground. Its source thus can be pulled high through the respective access transistor.
Each access transistor has its drain coupled to the source of the respective state transistor and thus to the gate of the complementary state transistor. The source of each access transistor is tied to a respective bit line which is shared by all cells in a column. Thus, each column of memory cells has a true bit line and a false bit line. The gates of the access transistors are coupled to each other and to a word (or subword) line. A voltage high on the word line closes the access transistors electrically coupling the bit lines and the respective state transistors.
During a read operation, the bit lines coupled to a selected cell are coupled to a sense amplifier, which must sense the relative voltages on the bit lines to determine the contents of the selected cell. Sense amplifiers, along with their associated circuitry, are relatively large devices so high density architectures multiplex several columns to a sense amplifier. A column is selected for "sensing" when the pass gate or transmission gate for each of its two bit lines are activated. The other columns sharing the sense amplifier are decoupled as their gates remain open. Thus, an address decoder can select a desired memory cell by activating the corresponding word and column lines (and block select lines in divided word architectures).
During each read operation, at least one bit line is high, and thus so is the associated data line between the respective pass gate and the associated sense amplifier. During the next read operation, this formerly high data line must fall to a suitably intermediate level so as to meet the threshold requirement to turn on the pass gate for the next read operation. Ideally, the data line would return to about 4 V between reads. However, capacitive loading of the data line limits the rate at which this level to be approached. However, with the control gate at 5 V, an NMOS pass gate begins to turn on at 4 V, so that the bit line can be read well before the ideal intermediate level is reached.
The finer feature dimensions that make possible higher density SRAMs are more vulnerable to perturbations and therefore voltage levels are more subject to fluctuations. When a power source slews to 4 V, a formerly high data line must drop below 3 V for a selected NMOS pass gate to turn on for a subsequent read operation. If reading is performed too soon, an error is likely to result. If timing is slowed to ensure proper data line recovery when power is 4 V, access times are slow.
This problem with NMOS column pass gates can be addressed by using, in their stead, transmission gates. A transmission gate includes a PMOS transistor in parallel with an NMOS transistor. When ground is applied to its control gate, the PMOS transistor closes at voltages more than 1 V above ground. Thus, the PMOS transistor provides the desired coupling in the cases that give the NMOS transistor trouble, and vice versa.
Offsetting the clear advantage of transmission gates, are their costs in device area, as well as in routing and processing complexity. Obviously, a transmission gate requires two transistors to perform the function performed by one transistor in a pass gate. The CMOS technology required to fabricated NMOS and PMOS circuits together is more complex than NMOS technology. Normally, p-type wells must be defined within an NMOS substrate. These wells must be sufficiently large to avoid parasitic losses between device types. Thus, the wells add to the required spacing between neighboring NMOS and PMOS transistors. The relatively large column transmission gates can limit the pitch of the columns they are associated with and thus the density of the memory cells.
Inverters are required to generate complementary control signals for the PMOS and NMOS transistors. This means that logic elements, namely inverters, must be fabricated along with each column transmission gate. A typical inverter comprises a PMOS transistor and an NMOS transistor with their drains coupled. A transmission gate plus inverter can require a pitch ten times that otherwise required by cell columns. Alteratively, the inverters can be outside the memory array, but then the number of control lines bussed through the array is doubled. Routing complexity then increases geometrically.
Thus, transmission gates address the speed limitations of SRAMs using NMOS pass gates at the expense of device density and related factors. What is needed is an SRAM architecture which provides for the densities comparable to those provided by NMOS column pass gates and which provides access speeds comparable to those provided using column transmission gates.